As semiconductor devices having metal-oxide-semiconductor (MOS) transistors become more highly integrated, the contact sizes and junction depths of the source/drain regions of these devices have been reduced. Accordingly, a salicide (self-aligned silicide) technique is widely used in the fabrication of highly integrated MOS transistor semiconductor devices in order to allow improvement in certain electrical characteristics of the MOS transistors such as the contact resistance of the source/drain regions. However, if metal silicide layers are formed on shallow source/drain junctions, the junction leakage current of the source/drain regions may be increased. Thus, the use of elevated source/drain structures has been proposed to help reduce and/or minimize the contact resistance. Such a technique is discussed in U.S. Pat. No. 6,440,807 to Ajmera et al.
FIGS. 1 to 3 are cross-sectional views illustrating a conventional method of fabricating a semiconductor device that is described in U.S. Pat. No. 6,440,807.
As shown in FIG. 1, a gate insulating layer 52 is formed on a semiconductor substrate 50. A polysilicon pattern 54 and a silicon nitride pattern 56 are sequentially stacked on the gate insulating layer 52. Sidewall spacers 60 are formed on sidewalls of the polysilicon pattern 54. The sidewall spacers 60 may be formed of silicon nitride. Source/drain regions 64 are formed in the semiconductor substrate 50 adjacent both sides of the polysilicon pattern 54. The source/drain regions 64 may be formed using an ion implantation process and an annealing process.
As shown in FIG. 2, an epitaxial layer 62 is grown on the source/drain regions 64 to provide elevated source/drain structures. The epitaxial layer 62 is not grown on the polysilicon pattern 54, since the polysilicon pattern 54 is surrounded by the silicon nitride pattern 56 and the insulating sidewall spacers 60. Then, as shown in FIG. 3, the silicon nitride pattern 56 is removed, and a metal silicide layer (not shown) may be formed on the polysilicon pattern 54 and the epitaxial layer 62 to lower the contact resistance of the polysilicon pattern 54 and the source/drain regions 64.
Even though the source/drain regions 64 may be formed to have a shallow junction depth, the elevated source/drain structures may provide sufficient junction depth to reduce and/or minimize the junction leakage current of the source/drain regions 64. Accordingly, by forming the metal silicide layer in the epitaxial layer 62, it may be possible to provide a device having a shallow junction depth and a relatively low contact resistance.
As noted above, epitaxial growth techniques may be used to form MOS transistors having elevated source/drain structures. However, if crystalline defects or contaminants exist at the surface of the substrate, it may be difficult to form a uniform epitaxial layer on the defective surface. For example, if impurity ions are implanted into a single crystalline semiconductor substrate, an amorphous layer may be formed at the surface of the substrate to a depth of, for example, about 300 angstroms. Such an amorphous layer may lead to an abnormal epitaxial layer. This may be particularly true in cases where P-type impurity ions are implanted into the semiconductor substrate.
As noted above, in the methods discussed in U.S. Pat. No. 6,440,807, the epitaxial layer is grown on source/drain regions that are formed using an ion implantation process and an annealing process. The ion implantation process typically generates crystalline defects or an amorphous layer at the surface of the substrate. Thus, U.S. Pat. No. 6,090,691 discloses a method of fabricating elevated source/drain structures without use of an epitaxial layer.
The crystalline defects, which are due to the ion implantation damage, can be reduced, minimized and/or eliminated by increasing the annealing process time or raising the annealing temperature. However, increasing the annealing process time and/or the annealing temperature tends to cause additional diffusion of the impurity ions in the extension regions which can lead to a short channel effect with the MOS transistor.